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Article Information

Practical issues in high speed PCB design
Sharawi, M.S.
Potentials, IEEE
Volume 23, Issue 2, April-May 2004 Page(s): 24 - 27
Digital Object Identifier 10.1109/MP.2004.1289994
Summary: Current high-speed PCB (printed circuit board) designs need extra care due to the frequency of operation and reduced rise time signals. We present the main issues and parameters that a PCB designer has to consider and analyze before a board layout is created. First order approximation equations for various parameters are presented, based on the geometry of the PCB traces. Some useful design practices are also mentioned. As the speed of operation increases, the variables that are neglected in the lower frequency/higher rise time situation become more significant. Such parameters increase the complexity of the design. Three-dimensional analysis becomes a must to calculate and model interconnects accurately. This is where field solvers and the role of the signal integrity engineer come into play.

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Volume 39 – September 2005

Download this article in PDF format. (516K)

A Practical Guide to High-Speed Printed-Circuit-Board Layout

By John Ardizzoni, (john.ardizzoni@analog.com)

Despite its critical nature in high-speed circuitry, printed-circuit-board (PCB) layout is often one of the last steps in the design process. There are many aspects to high-speed PCB layout; volumes have been written on the subject. This article addresses high-speed layout from a practical perspective. A major aim is to help sensitize newcomers to the many and various considerations they need to address when designing board layouts for high-speed circuitry. But it is also intended as a refresher to benefit those who have been away from board layout for a while. Not every topic can be covered in detail in the space available here, but we address key areas that can have the greatest payoff in improving circuit performance, reducing design time, and minimizing time-consuming revisions.

Although the focus is on circuits involving high-speed op amps, the topics and techniques discussed here are generally applicable to layout of most other high-speed analog circuits. When op amps operate at high RF frequencies, circuit performance is heavily dependent on the board layout. A high-performance circuit design that looks good “on paper」 can render mediocre performance when hampered by a careless or sloppy layout. Thinking ahead and paying attention to salient details throughout the layout process will help ensure that the circuit performs as expected.

The Schematic
Although there is no guarantee, a good layout starts with a good schematic. Be thoughtful and generous when drawing a schematic, and think about signal flow through the circuit. A schematic that has a natural and steady flow from left to right will tend to have a good flow on the board as well. Put as much useful information on the schematic as possible. The designers, technicians, and engineers who will work on this job will be most appreciative, including us; at times we are asked by customers to help with a circuit because the designer is no longer there.

What kind of information belongs on a schematic besides the usual reference designators, power dissipations, and tolerances? Here are a few suggestions that can turn an ordinary schematic into a superschematic! Add waveforms, mechanical information about the housing or enclosure, trace lengths, keep-out areas; designate which components need to be on top of the board; include tuning information, component value ranges, thermal information, controlled impedance lines, notes, brief circuit operating descriptions … (and the list goes on).

Trust No One
If you’re not doing your own layout, be sure to set aside ample time to go through the design with the layout person. An ounce of prevention at this point is worth more than a pound of cure! Don’t expect the layout person to be able to read your mind. Your inputs and guidance are most critical at the beginning of the layout process. The more information you can provide, and the more involved you are throughout the layout process, the better the board will turn out. Give the designer interim completion points—at which you want to be notified of the layout progress for a quick review. This “loop closure」 prevents a layout from going too far astray and will minimize reworking the board layout.

Your instructions for the designer should include: a brief description of the circuit’s functions; a sketch of the board that shows the input and output locations; the board stack up (i.e., how thick the board will be, how many layers, details of signal layers and planes—power, ground, analog, digital, and RF); which signals need to be on each layer; where the critical components need to be located; the exact location of bypassing components; which traces are critical; which lines need to be controlled-impedance lines; which lines need to have matched lengths; component sizes; which traces need to kept away from (or near) each other; which circuits need to be kept away from (or near) each other; which components need to be close to (or away from) each other; which components go on the top and the bottom of the board. You’ll never get a complaint for giving someone too much information—too little, yes; too much, no.

A learning experience: About 10 years ago I designed a multilayer surface-mounted board—with components on both sides of the board. The board was screwed into a gold-plated aluminum housing with many screws (because of a stringent vibration spec). Bias feed-through pins poked up through the board. The pins were wire-bonded to the PCB. It was a complicated assembly. Some of the components on the board were to be SAT (set at test). But I hadn’t specified where these components should be. Can you guess where some of them were placed? Right! On the bottom of the board. The production engineers and technicians were not very happy when they had to tear the assembly apart, set the values, and then reassemble everything. I didn’t make that mistake again.
Location, Location, Location
As in real estate, location is everything. Where a circuit is placed on a board, where the individual circuit components are located, and what other circuits are in the neighborhood are all critical.

Typically, input-, output-, and power locations are defined, but what goes on between them is “up for grabs.」 This is where paying attention to the layout details will yield significant returns. Start with critical component placement, in terms of both individual circuits and the entire board. Specifying the critical component locations and signal routing paths from the beginning helps ensure that the design will work the way it’s intended to. Getting it right the first time lowers cost and stress—and reduces cycle time.

Power-Supply Bypassing
Bypassing the power supply at the amplifier’s supply terminals to minimize noise is a critical aspect of the PCB design process—both for high-speed op amps and any other high-speed circuitry. There are two commonly used configurations for bypassing high-speed op amps.

Rails to ground: This technique, which works best in most cases, uses multiple parallel capacitors connected from the op amp’s power-supply pins directly to ground. Typically, two parallel capacitors are sufficient—but some circuits may benefit from additional capacitors in parallel.

Paralleling different capacitor values helps ensure that the power supply pins see a low ac impedance across a wide band of frequencies. This is especially important at frequencies where the op-amp power-supply rejection (PSR) is rolling off. The capacitors help compensate for the amplifier’s
For high bandwidth trans-continental links this seriously limits the maximum transfer speed per TCP connection.


GlobalSpec, Inc.
No portion of this site may be copied, retransmitted, reposted, duplicated or otherwise used
without the express written permission of GlobalSpec Inc. 350 Jordan Rd, Troy, NY, 12180
Advanced High Speed Digital Design and PCB Layout
This two and 1/2-day course is tailored to the high-speed digital design engineer who wants to go a step beyond and delve into a deeper understanding of high-speed phenomena. With edge rates ever decreasing and clock rates becoming faster, it is vital that engineers understand the underlying issues of the transmission line to insure signal integrity. Also, bypassing these higher frequency edge rates and the ever-increasing power of today抯 FPGAs and micros require a better graps of signal power switching. PCBs are becoming more complex with finer traces and spaces and more layers with more blind and buried vias. This requires more attention to controlling crosstalk, EMI, impedance control. This course will cover 1) all transmission line loss concepts including the four performance regions; 2) PCB effects for high-speed transmission; 3) bypassing high edge rate/high power ICs; 4) advanced concepts of singled-ended and differential signaling and 5) how to overcome eye closure for high speed, long haul transmission media (backplanes, motherboards, and connectors/cables). These and many more issues are presented along with solutions that the leading edge companies are using to solve the ever-increasing sophistication of today抯 state of the art designs.

This and all other courses are available as On Site Training
WHAT THE COURSE COVERS:
Advanced High Speed Concepts
Impedance of structures to both clock rate harmonics and edge rate harmonics
Resonance on Transmission Lines: Serial and Parallel resonance. Quarter wave length differences of high and low end impedance termination.
Near field and far field definitions and their effects on the magnetic and electric field strengths
The quality factor for lumped circuitry: Why they can ring, crosstalk and cause EMI radiation


Transmission Lines (TL)
The TL Cell-Defining, Rdc, Rac, Skin Effect, Proximity, and the Dielectric Loss
Current Travel on TLs: Converting the B field to eddy currents and how it creates the skin effect and proximity effect
Characteristics of PCB Material: What material is used for high frequency: DF, Cost, DFM, DFA


Performance Regions
The basic RLGC cell and its effect on rising and falling edges
The Lumped Element region-parameters and model
Practical applications of the lumped model
The RC Region of the lumped model. Input/characteristic/Output impedance. Propagation velocity, Elmore抯 delay and lumped model algorithm
The Constant Loss Region: Boundary Conditions, propagation coefficient, resonance, termination considerations
The Skin Effect Region: Boundary Conditions, characteristic impedance, propagation delay parameters, termination options, speed and distance
Dielectric Region: Boundary Conditions, characteristic impedance, dielectric loss/tangent loss, propagation delay, resonance, termination


The Printed Circuit Board (PCB)
Modeling PCB Traces
Skin Effect and Dielectric Loss for PCB Traces: microstrip and stripline
Dielectric Properties, relative costs and core/prepreg issues for high speed stackups
Effects of temperature, frequency and mfg tolerance on characteristic impedance
Solder Mask and Conformal Coating: effects on Z0, propagation delay and impedance equations
Matching Capacitive and inductive loads using trace width modification
Far end and Near end Crosstalk: Inductive and capacitive for microstrips and striplines
Matching traces to connectors: Minimizing reflections, crosstalk and EMI
Vias: C and L of vias (through hole, blind, buried), via discontinuities and eliminating reflections of vias
AC Biasing for End Terminators, where should it be used and how to choose the capacitor
Hairball networks, bifurcated lines and capacitive stubs
Terminating differentials - Eliminating common mode and minimizing power
What causes differentials unbalance?
Diode and active terminators, Resistor Selection and Crosstalk in Terminators
Capacitance & Inductance of Vias
Return Current and Its Relation to Vias
Through Hole, Blind, Buried, Micro Vias
Intelligent Vias and autorouters
Via discontinuity and via resonance concerns


Advanced Topics in Bypassing
Shoot through current and die capacitance
Eliminating mode conversion
Why the 0201, the long electrode and the Y cap may be essential to control switching impedance and EMI radiation
Breakout and bypassing the 4, 5, 6 perimeter ring and fully populated BGA
Do copperfills (pours) really help in bypassing?
What is the present status of innerplane C materials (FR4, ceramic filled, and polymide) and how thin can they practically be made?
How much C is needed and layout considerations for today抯 FPGAs and micros?
Return current and intelligent via placement


Differential Signaling
Attributes/drawbacks of loosely/tightly coupled differential pairs
Definition and examples of differential and common mode V and I
Differential impedance: Odd and even modes
Advantages and disadvantages of Edge (side by side), Broadside (dual), asymmetric, and microstrip differentials
Reflections and crosstalk in differentials. Metastability, Clk skew, driver skew, bit pattern sensitivity, ISI, skin effect and dielectric constant. Jitter, BER, and the eye diagram
Matching electrical lengths

This course includes the course text book over 275-pages in length and in color of book class notes.
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Embedded.com > Design Articles


The HDMI Design Guide to high-speed PCB design in HDTV receiver applications

By Kugelstadt, Senior Systems Engineer, Texas Instruments
Digital TV Designline
(11/07/07, 12:30:00 H EST)
Introduction
This article presents design guidelines for helping users of HDMI mux-repeaters to maximize the device's full performance through careful printed circuit board (PCB) design. We'll explain important concepts of some main aspects of high-speed PCB design with recommendations. This discussion will cover layer stack, differential traces, controlled impedance transmission lines, discontinuities, routing guidelines, reference planes, vias and decoupling capacitors.
Layer stack
The pin-out of a HDMI mux-repeater is tailored for the design in HDTV receiver circuits (see Figure 1). Each side of the package provides a HDMI port, featuring four differential TMDS signal pairs, thus resulting in three input and one output port. The remaining signals comprise the supply rails, Vcc and ground, and lower speed signals such as the I2C interface, Hotplug-detect and the mux-selector pins.

Figure 1. The device pin-out is tailored for HDTV receiver applications
A minimum of four layers are required to accomplish a low EMI PCB design (see Figure 2). Layer stacking should be in the following order (top-to-bottom): TMDS signal layer, ground plane, power plane and control signal layer.


High-speed circuitry is used in all modern products. Understanding high-speed fundamentals and the relationship of speed to distance and how to apply this knowledge is the key to successful designing. Any significant noise problems at the system level can be very expensive and must be solved at the board level during layout. But yet board costs must be managed properly. It is easy to over-design a product, have unnecessary layers and drive the cost of a product up too high.

In this course the focus is on what must be understood to take the schematic and transform it in

decreasing PSR. Maintaining a low impedance path to ground for many decades of frequency will help ensure that unwanted noise doesn’t find its way into the op amp. Figure 1 shows the benefits of multiple parallel capacitors. At lower frequencies the larger capacitors offer a low impedance path to ground. Once those capacitors reach self resonance, the capacitive quality diminishes and the capacitors become inductive. That is why it is important to use multiple capacitors: when one capacitor’s frequency response is rolling off, another is becoming significant, thereby maintaining a low ac impedance over many decades of frequency.




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FreeBSD Quarterly Status Reportto a working PCB design while keeping costs under control. Emphasis is on digital circuits, though it also is just as applicable to analog. Information presented in this course can be applied to high-speed digital and analog designs up into the GHz range.

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2) Substrate Materials & Fabrication
The successful design, when high-speed circuits are present, must focus on the materials the signals have to transmit through. In this section information is presented about board material, dielectric constant values, the effects of frequency, core material types and thickness, prepreg and thickness, resin, moisture effects, copper foil, fabrication panels, layer stack-ups, fabrication process, copper weight and resistance, copper losses, test coupons, TDR measurements, velocity and propagation delays for different layers, dissipation factor and variances.
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high speed pcb design,high frequency differencial LDVS Electronics circuit PCB board design,low cost shenzhen,cn china